OVERLAPPING DOT PRINTER

PURPOSE:To obtain characters having high quality by means of a simple head by mounting a circuit, which does not conduct overlapping to characters of which the concentration of dot density of an original pattern is remarkable, to a dot printer which uses the original pattern as an investigating poin...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	SAKAI HIROSHI, UJIIE MASAMI
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING CORRECTION OF TYPOGRAPHICAL ERRORS COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY HANDLING RECORD CARRIERS i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME IMAGE DATA PROCESSING OR GENERATION, IN GENERAL LINING MACHINES PERFORMING OPERATIONS PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION PRESENTATION OF DATA PRINTING RECOGNITION OF DATA RECORD CARRIERS SEALS SELECTIVE PRINTING MECHANISMS STAMPS TRANSPORTING TYPEWRITERS
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Beschreibung
Zusammenfassung:	PURPOSE:To obtain characters having high quality by means of a simple head by mounting a circuit, which does not conduct overlapping to characters of which the concentration of dot density of an original pattern is remarkable, to a dot printer which uses the original pattern as an investigating point and inserts dots around the point as interpolation points. CONSTITUTION:Arithmetic operation ABCD is executed because A, B, C, D are inputted to the input of an AND gate G1, and interpolation not conducted because 1 is outputted from an OR gate G9 when the result is 1. Arithmetic operation A'B'C'D' is executed because A', B', C', D' are inputted to an AND gate G2, and the result is added to one of the input of an AND gate G8. In inhibit gates G3-G6, on the other hand, the arithmetic operation of ACD, ABD, ABC and BCD is executed to each, and the result is added to the other of the input of the AND gate G8 through an OR gate G7 when even only one among them is 1. Consequently, 1 is outputted from the AND gate G8, and outputted from the OR gate G9. Accordingly, interpolation is not conducted.