CMOS 3-STATE CIRCUIT

CMOS 3-STATE CIRCUIT

PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KODAMA TAROU, IWASAKI TOMONOBU
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KODAMA TAROU
IWASAKI TOMONOBU
description PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS inverter 11 consisting of transistors TRT1 and T2 of an output stage, a p channel TRT3 put between the TRT1 and a power supply VCC to set an output OUT in an HZ (high impedance) state, and n channel MOSTRT4 put between a point A and an earth. The TRs T3 and T4 are controlled by the 3-state control signal CTL.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS58221520A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS58221520A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS58221520A3</originalsourceid><addsrcrecordid>eNrjZBBx9vUPVjDWDQ5xDHFVcPYMcg71DOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmFkZGhqZGBo7GxKgBAGtIHqs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CMOS 3-STATE CIRCUIT</title><source>esp@cenet</source><creator>KODAMA TAROU ; IWASAKI TOMONOBU</creator><creatorcontrib>KODAMA TAROU ; IWASAKI TOMONOBU</creatorcontrib><description>PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS inverter 11 consisting of transistors TRT1 and T2 of an output stage, a p channel TRT3 put between the TRT1 and a power supply VCC to set an output OUT in an HZ (high impedance) state, and n channel MOSTRT4 put between a point A and an earth. The TRs T3 and T4 are controlled by the 3-state control signal CTL.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>1983</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19831223&amp;DB=EPODOC&amp;CC=JP&amp;NR=S58221520A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19831223&amp;DB=EPODOC&amp;CC=JP&amp;NR=S58221520A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KODAMA TAROU</creatorcontrib><creatorcontrib>IWASAKI TOMONOBU</creatorcontrib><title>CMOS 3-STATE CIRCUIT</title><description>PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS inverter 11 consisting of transistors TRT1 and T2 of an output stage, a p channel TRT3 put between the TRT1 and a power supply VCC to set an output OUT in an HZ (high impedance) state, and n channel MOSTRT4 put between a point A and an earth. The TRs T3 and T4 are controlled by the 3-state control signal CTL.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1983</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBBx9vUPVjDWDQ5xDHFVcPYMcg71DOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmFkZGhqZGBo7GxKgBAGtIHqs</recordid><startdate>19831223</startdate><enddate>19831223</enddate><creator>KODAMA TAROU</creator><creator>IWASAKI TOMONOBU</creator><scope>EVB</scope></search><sort><creationdate>19831223</creationdate><title>CMOS 3-STATE CIRCUIT</title><author>KODAMA TAROU ; IWASAKI TOMONOBU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS58221520A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1983</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>KODAMA TAROU</creatorcontrib><creatorcontrib>IWASAKI TOMONOBU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KODAMA TAROU</au><au>IWASAKI TOMONOBU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CMOS 3-STATE CIRCUIT</title><date>1983-12-23</date><risdate>1983</risdate><abstract>PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS inverter 11 consisting of transistors TRT1 and T2 of an output stage, a p channel TRT3 put between the TRT1 and a power supply VCC to set an output OUT in an HZ (high impedance) state, and n channel MOSTRT4 put between a point A and an earth. The TRs T3 and T4 are controlled by the 3-state control signal CTL.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS58221520A
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title CMOS 3-STATE CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T02%3A00%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KODAMA%20TAROU&rft.date=1983-12-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS58221520A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true