CMOS 3-STATE CIRCUIT

PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KODAMA TAROU, IWASAKI TOMONOBU
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To decrease the layout area, by decreasing the number of elements per circuit of a CMOS 3-state circuit. CONSTITUTION:An NOR gate is shared by all 3-state circuits. Each 3-state circuit is provided with a CMOS inverter 12 which inverts and amplifies data DIN, a transmission gate 3, a CMOS inverter 11 consisting of transistors TRT1 and T2 of an output stage, a p channel TRT3 put between the TRT1 and a power supply VCC to set an output OUT in an HZ (high impedance) state, and n channel MOSTRT4 put between a point A and an earth. The TRs T3 and T4 are controlled by the 3-state control signal CTL.