INTEGRATED CIRCUIT

PURPOSE:To select a logical output in a resetting period optionally by connecting an additional circuit which has high output impedance during the resetting period to the output side of the output port register of a logical output impedance IC. CONSTITUTION:When a reset pulse RS is supplied to a terminal 6 after power-on operation, a data signal DT is supplied from a computer 1 to the input register 3 of a latch IC2 for extension, but it is not transferred to the output register 4. The Q output of an FF circuit 9 is on a level L, so the respective NAND circuits 10 and NAD circuits 11 of logical circuits 8 (i=0-n-1) of the additional circuit 7 are closed and the outputs of the circuits 10 and 11 are on the levels H and L respectively. Therefore, MOSFETs 12 and 13 are both off and high output impedance is obtained at each terminal T3; and terminals connected to a power source B through a resistance 11 or grounded are on the levels H and L respectively and terminals in a floating state sill have the high impedance. Output terminals 10n and 10n+1 are set on the level H or L optionally.