BUS ALLOTMENT CONTROLLING SYSTEM

PURPOSE:To give an equal bus occupying right to each CPU, by connecting plural secondary CPUs to a single primary CPU via a common bus and applying successively signals of H levels to the secondary CPUs from a counter. CONSTITUTION:Secondary CPU1-3 are connected to a primary CPU4 with buses 5 and 6. A counter 7 delivers 71-73 the output of an oscillator 8 in a short period t1 and feeds the output to AND gates 9-11. For instance, an AND gate 9 is turned on when a bus occupying request RQ1 of the CPU1 overlaps a counter output C1. Then an OR12 is given to the gate 9, and a signal RQ0 is supplied to the CPU4. Then the counter 7 is stopped for a period longer than the period t1 with a signal S. At the same time, the signal S is supplied also to an FF14. The CPU4 supplies its rise to the FF14 by an answer signal AV0 and sends a signal AV1 to the CPU1 for occupation of the bus. After the lapse of a fixed time, the fall of the signal AV0 is differentiated. Then the signal AV0 is supplied to the FF14 to stop the signal AV1. Thus each secondary CPU can equally have a chance to occupy the bus.