ASYNCHRONOUS PROCESSOR

PURPOSE:To eliminate the waiting time for transfer of a signal and to prevent an omission in fetching data, by forming reading and writing states by a scanner counter of a clock counter, and processing the asynchronous data on the basis of said reading and writing states. CONSTITUTION:A data selector 41 supplies data in time division to a storage circuit 42 from each of digital signal generators DSG10-1n on the basis of a scanner address signal which is supplied from a clock counter 46 via a bus 105. A control circuir 45 supplies a writing signal W to the circuit 42, and an address gate 44 supplies a scanner address signal to the circuit 42 respectively. A digital signal processor DSR2 delivers a frame address of the desired data to the circuit 42 via the gate 44 and the circuit 45 and stores 42 a reading signal R to latch 43 a latching signal. The gate 44 delivers the scanner address signal to the circuit 42 and transfers data of DSG10-1n to the DSR2. In such a way, the asynchronous data is processed.