CONNECTION SYSTEM OF MULTIPROCESSOR

PURPOSE:To ensure the assured transfer of data and at the same time to reduce the time of process as well as to increase the process capacity, by carring out the transfer of data between a master processor and each subprocessor with the clock signal in good order nad with highefficiency. CONSTITUTION:The clock signal CL which is turned to 1 and 0 in the 1st and 2nd periods respectively is applied to a master processor MPU in the form of an interruption signal IRQ. At the same time, gates MG1 and MG2 are opened. While 1 of the signal CL is inverted by an inverter INV to O. Thus no interruption IRQ is carried out to a subprocessor SPU#O, and tages SG1 and SG2 are closed. And an acceess is inhibited to a radom memory RAM from subprocessors SPUs#O-#n via a sub-bus SB. Then the master processor MPU gives an access to the memory RAM via a main bus MB plus the gates MG1 and MG2. When the signal CL is set at O, the gates MG1 and MG2 are closed with the gates SG1 and SG2 opened. And the processor SPU#O receives an interruption IRQ.