PLL SYNTHESIZER RECEIVER

PURPOSE:To increase the frequency stability, by constituting the 1st and 2nd local oscillator with PLL circuits. CONSTITUTION:The output of the 1st local oscillator 3 is applied to a variable frequency divider 8, frequency-divided according to a frequency dividing code N1 outputted from a channel selection control section 26, phase is compares with the output of a reference frequency generator 9 at a phase comparator 10 and applied to the 1st local oscillator 3 via a filter 11. The output of an oscillator 12 is mixed with the output of a reference frequency oscillator 14 at a mixer 17 for frequency conversion, applied to a variable frequecy divider 19 via a filter 18, and the frequency of the oscillator 12 is controlled in the same way as the 1st PLL circuit 23. On the other hand, the output of the oscillator 12 is frequency-divided to 1/M with a frequency divider 13 and mixed with the output of the reference frequency oscillator 14 with the mixer 15 and applied to the 2nd mixer 5 of the signal reception system via a filter 16. Thus, the minimum frequency interval changeable for the 2nd local oscillator 25 can be made to 1/M of the minimum frequency interval lockable at the 2nd PLL circuit 26.