PLL SYNTHESIZER RECEIVER

PURPOSE:To increase the frequency stability with simple constitution. CONSTITUTION:The output of the 1st local oscillator 13 is ampplied to a PLL circuit 14, and control is made so that the output frequency of the 1st local oscillator 13 is NF1 with the frequency dividing ratio code N outputted from a channel selction control section 21 and the control output of the PLL circuit 14. The output of the oscillator 15 is applied to a PLL circuit 16, and control is made so that the frequency of the oscillator 15 is nF2 with the frequency dividing ratio code n outputted from the channel selection control section 21 and the control output of the PLL circuit 16. The output of the oscillator 15 is frequency-divided to 1/M with a fixed frequency divider 17, the result is mixed and frequency-converted with an output frequency fx of a reference frequency oscillator 19 by means of a mixer 18, and applied to the 2nd mixer 5 in a signal path. Thus, the minimum frequency interval changeable by the 2nd local oscillation frequency is 1/M of the minimum frequency interval lockable at the 2nd PLL circuit 23, allowing the oscillation frequency of the 1st PLL circuit 22 and the 2nd PLL circuit 23 to be continuously controlled.