PROGRAMMABLE BAUD RATE GENERATOR

PURPOSE:To set transfer speeds which correspond to data terminals by executing a simple program. CONSTITUTION:An output line from the output port 1 of a microcomputer is connected to a latch circuit 2. An address bus from a CPU is connected to an address setting circuit 3, which detects an address t...

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Bibliographische Detailangaben
1. Verfasser:	KAGEYAMA KAZUO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	PURPOSE:To set transfer speeds which correspond to data terminals by executing a simple program. CONSTITUTION:An output line from the output port 1 of a microcomputer is connected to a latch circuit 2. An address bus from a CPU is connected to an address setting circuit 3, which detects an address to drive the latch circuit 2. A decoder 4 sets two transfer speeds for a binary-coded data signal sent through the latch circuit 2. For example, it decodes it into hexadecimal-coded data to set a channel 1 and a channel 1. A gate ciruit 6 specifies the numbers of channels whose transfer speeds are set. The output of a clock oscillator 7 is supplied through a frequency dividing circuit 8 to an output driver 9, and an output signal whose data signal speed of each baud rate is set is outputted to the specified channels.