SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To obtain a high-speed ternary output circuit by applying a ternary control input to an inverter composed of enhancement N type FETs for output through a complementary MISNOR gate. CONSTITUTION:A data input terminal 1 is connected to the gate of a complementary MIS inverterI. Drains of FETs...

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Bibliographische Detailangaben
1. Verfasser:	NAKAMURA ITSUO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	PURPOSE:To obtain a high-speed ternary output circuit by applying a ternary control input to an inverter composed of enhancement N type FETs for output through a complementary MISNOR gate. CONSTITUTION:A data input terminal 1 is connected to the gate of a complementary MIS inverterI. Drains of FETs T1 and T2 are connected to the input of a complementary MISNOR gate II. The input terminal of a complementary MISNOR gate III is connected to the terminal 1, and the outputs of the gates II and III are connected to enhancement N tpe FETs T12 and T13. A ternary controlling input is supplied to a terminal 2. Since the FETs T12 and T13 are used as load elements constituting an output inverter, channel conductance is increased and a rise time is shortened.