ERROR RECOVERY SYSTEM OF LOGICAL DEVICE

PURPOSE:To recover a fixed fault, by processing by use of a CPU having no error succeedingly, the processing which has been executed by a faulty CPU, at each instruction unit. CONSTITUTION:When an instruction is executed in a CPU10, information of a program controllable register group 130 before exe...

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Bibliographische Detailangaben
Hauptverfasser: KIMIJIMA KOUJI, TOMITA KATSUICHI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To recover a fixed fault, by processing by use of a CPU having no error succeedingly, the processing which has been executed by a faulty CPU, at each instruction unit. CONSTITUTION:When an instruction is executed in a CPU10, information of a program controllable register group 130 before executing the instruction is waited in a stand-by register group 140 whenever one instruction is executed. A retry controlling circuit 260 for the CPU10 on a CPU20 monitors whether retry is executed or not at every instruction. When it is informed to the CPU10 from the retry controlling circut 260 that a recovery impossible error has been detected, an execution controlling circuit 210 of the CPU20 generates an instruction, and informs the control program of a recovery request of the CPU10. The control program halts the processing which is being executed, and executes its transfer. An inter-register shift controlling circuit 270 shift the information to the stand-by register group 240 of the CPU20 from the stand-by regiter group 140 of the CPU10.