METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | KONDOU KAZUHIRO |
| description | PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N1 has a terminal A1 connectable to an outer power line pattern at a first area at the top end shown by a triangle and terminal A2 connectable to an inner power line pattern L1 at a second area below it shown by a triangle. A second node pattern N2 has a terminal B1 connectable to an outer ground line pattern at a first area at the top end shown by a triangle and terminal B2 connectable to an inner ground line pattern L2 at a second area below it shown by a triangle. This allows an semiconductor integrated circuit to be designed, using one kind of I/O cell pattern, irrespective of the number of different voltage sources. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH1140674A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH1140674A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH1140674A3</originalsourceid><addsrcrecordid>eNrjZDDxdQ3x8HdR8HdTcHEN9nT38_RzVwh29fV09vdzCXUO8Q9S8PQLcXUPcgxxdVFw9gxyDvUM4WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BHoaGJgZm5iaOxkQoAQCMxSdQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>KONDOU KAZUHIRO</creator><creatorcontrib>KONDOU KAZUHIRO</creatorcontrib><description>PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N1 has a terminal A1 connectable to an outer power line pattern at a first area at the top end shown by a triangle and terminal A2 connectable to an inner power line pattern L1 at a second area below it shown by a triangle. A second node pattern N2 has a terminal B1 connectable to an outer ground line pattern at a first area at the top end shown by a triangle and terminal B2 connectable to an inner ground line pattern L2 at a second area below it shown by a triangle. This allows an semiconductor integrated circuit to be designed, using one kind of I/O cell pattern, irrespective of the number of different voltage sources.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990212&DB=EPODOC&CC=JP&NR=H1140674A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990212&DB=EPODOC&CC=JP&NR=H1140674A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KONDOU KAZUHIRO</creatorcontrib><title>METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N1 has a terminal A1 connectable to an outer power line pattern at a first area at the top end shown by a triangle and terminal A2 connectable to an inner power line pattern L1 at a second area below it shown by a triangle. A second node pattern N2 has a terminal B1 connectable to an outer ground line pattern at a first area at the top end shown by a triangle and terminal B2 connectable to an inner ground line pattern L2 at a second area below it shown by a triangle. This allows an semiconductor integrated circuit to be designed, using one kind of I/O cell pattern, irrespective of the number of different voltage sources.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxdQ3x8HdR8HdTcHEN9nT38_RzVwh29fV09vdzCXUO8Q9S8PQLcXUPcgxxdVFw9gxyDvUM4WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BHoaGJgZm5iaOxkQoAQCMxSdQ</recordid><startdate>19990212</startdate><enddate>19990212</enddate><creator>KONDOU KAZUHIRO</creator><scope>EVB</scope></search><sort><creationdate>19990212</creationdate><title>METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>KONDOU KAZUHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH1140674A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KONDOU KAZUHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KONDOU KAZUHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>1999-02-12</date><risdate>1999</risdate><abstract>PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N1 has a terminal A1 connectable to an outer power line pattern at a first area at the top end shown by a triangle and terminal A2 connectable to an inner power line pattern L1 at a second area below it shown by a triangle. A second node pattern N2 has a terminal B1 connectable to an outer ground line pattern at a first area at the top end shown by a triangle and terminal B2 connectable to an inner ground line pattern L2 at a second area below it shown by a triangle. This allows an semiconductor integrated circuit to be designed, using one kind of I/O cell pattern, irrespective of the number of different voltage sources.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JPH1140674A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T00%3A51%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KONDOU%20KAZUHIRO&rft.date=1999-02-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH1140674A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |