SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To improve the electrostatic destruction strength of NC(non-connection) pins in a logic LSI which adopts a master slice system. SOLUTION: In a CMOS gate array, a bonding pad corresponding to a signal input cell and a bonding pad corresponding to a power input cell are constituted of the conductive layers of three layers. A bonding pad corresponding to an I/O cell 3c, which is not used is constituted only of conductive layer 70b of the highest layer. Thus, a film thickness (11) at a lower part in a bonding pad (NC pad) BP, corresponding to an I/O cell 3c which is not used, is thicker than those of the signal bonding pad BP and the power bonding pad BP, and a distance with a semiconductor substrate 1 becomes larger.