SEMICONDUCTOR APPARATUS

PROBLEM TO BE SOLVED: To shorten the cycle time of reading, writing of a dynamic memory cell by selecting a word line, reading out a signal of a corresponding memory cell to a plurality of corresponding bit lines, amplifying the signal on an input/ output line and precharging a plurality of the bit...

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Bibliographische Detailangaben
Hauptverfasser: AYUKAWA KAZUSHIGE, SUGANO YUSUKE, MIZUNO HIROYUKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To shorten the cycle time of reading, writing of a dynamic memory cell by selecting a word line, reading out a signal of a corresponding memory cell to a plurality of corresponding bit lines, amplifying the signal on an input/ output line and precharging a plurality of the bit lines. SOLUTION: At a write operation, as only a word line of a selected memory cell is asserted, a bit line is driven in accordance with write data immediately after the word line is asserted. A destructively read data from a dynamic memory is stored in an entry of a cache memory 110. Since a Valid bit is set when the data is sent (replaced) out of the cache memory, the data is written back to the dynamic memory. The data merely reciprocates between the dynamic memory 100 and cache memory 110 via a bus controller 116 and therefore the original data is not lost.