CIRCUIT AND METHOD FOR POLYPHASE CLOCK GENERATION

PROBLEM TO BE SOLVED: To provide a polyphase clock generating circuit and its method which are strong against noises, generate a polyphase clock that equally splits one cycle of an input clock signal and can easily generate the polyphase clock even with respect to a fast clock signal. SOLUTION: This device has an input side M frequency divider circuit 2 for outputting an input side M frequency division clock signal 7 and a reset signal 6 and an output side M frequency devider circuit 3, to which a reset signal 9 accompanying a specified delay outputted from a clock generating part 1 is inputted, which outputs an output side M frequency division clock signal 10 by M frequency dividing an output clock signal 8, synchronously with the inputted delayed reset signal 9. By having the input side M frequency division clock signal 7 compared with the output side M frequency division clock signal 10, the delay amount of a clock generating part 1 is controlled.