CACHE MEMORY

PROBLEM TO BE SOLVED: To reduce the degradation of the throughput due to snooping of a cache memory and to shorten the time required for initialization in a multi- processor system. SOLUTION: Each of cache memories 30A (30A1 , 30A2 ,...) has two directory part 32 (321 , 322 ,...) and 34 (341 , 342 ,...) where a V bit indicating whether every storage block of data array parts 31 (311 , 312 ,...) is valid or not, and a corresponding address of a main storage is stored. If an access request is outputted to a system bus 3 because of the absence of required data, for example, in the data array part 312 of a processor 1A2 , a bus control part 401 of the processor 1A1 checks the directory part 341 without passing an internal bus 201 . Only when data, which are valid and have been rewritten, exist in the data array part 321 , the data are outputted to the system bus 3 through the internal bus 201 . At the time of initialization, V bits n directory parts 32 and 34 are rewritten with initial values by bus control parts 40 (401 , 402 ,...) as hardware.