CLOCK DELAY AMOUNT CONTROL METHOD

PROBLEM TO BE SOLVED: To automatically adjust a latch clock at an input side LSI in the case of high-speed inter-LSI data transfer while using data themselves so as to satisfy setup time and hold time. SOLUTION: Concerning a system for adjusting the clock of data input latch 21 for latching transfer data between LSI while using a data transfer path itself, this system is provided with a delay amount control period (in which TUNE is outputted) and a data transfer period, the transfer data are outputted from the data output side LSI during the delay amount control period so as to be changed from Lo (Hi) to Hi (Lo) and when the data latched at the data input side LSI are Lo (Hi), the value of flip-flop 2412 for holding the delay amount is increased but when they are Hi (Lo), the value of flip-flop 2412 is adjusted to be decreased. During the data transfer period, the clock of controlled delay amount is further delayed for a fixed amount by a delay circuit 2416.