SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST CIRCUIT TO BE COMPRISED THEREIN

PROBLEM TO BE SOLVED: To secure a semiconductor integrated circuit and a test circuit to be comprised therein, capable of testing a wide range of subject circuits. SOLUTION: A semiconductor integrated circuit is used after converting it into a test mode through power input from a test terminal. When...

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1. Verfasser: OKAYASU HIDEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To secure a semiconductor integrated circuit and a test circuit to be comprised therein, capable of testing a wide range of subject circuits. SOLUTION: A semiconductor integrated circuit is used after converting it into a test mode through power input from a test terminal. When it is turned to the test mode, a clock highly speeded up at nth-fold by a clock multiplicational circuit 2 is inputted into a subject circuit 1, and further, data are inputted through a signal multiplied as far as nth-fold by a data compression circuit 3. Since the subject circuit 1 is inputted with the clock and the data multiplied as far as nth-fold, in the case where the subject circuit 1 is operable at the clock at more nth-fold than a test circuit input clock, it is normally operated, and thereby normal compression data are outputted. The compression data outputted after being compressed at more nth-fold than the subject circuit 1 is converted into 1/n by a compression data depression circuit 4, and thus observation at a large scale integrated circuit tester is made possible to be done.