METHOD FOR DETERMINING INTERCONNECTION PATTERN OF INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To determine an interconnection rule based on evaluation results reflecting actual circuit information in the initial development stage of a process and design environment. SOLUTION: In an interconnection pattern extracting process 15 and a transistor extracting process 16, a designated interconnection, an interconnection contiguous thereto and a transistor to be connected with the designated interconnection are extracted. In an interconnection pattern modifying process 17 and a transistor size modifying process 18, a reduction rate of the circuit area is then estimated according to a new design rule 15 of a next generation process and the interconnection width or the transistor size are modified according to the estimation. Subsequently, a layout corresponding to the new design rule 15 is generated and the interconnection resistance R and capacitance C are calculated for the generated layout using process parameters 19 in an interconnection RC calculating process 20. Finally, the time lag or power consumption is calculated for the designated interconnection and employed for evaluating the interconnection pattern or the structure.