MANUFACTURE OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To permit reduction in pattern size by reducing pattern-overlapping allowance. SOLUTION: In this method, a gate oxide film 3 is formed first on a Si substrate 1. Next, a first connecting hole 5 is formed to the oxide film 3. Thereafter, a first wiring layer 9 is formed within the connecting hole 5. Next, a first wiring layer 9 in the connecting hole 5 is partly removed. Subsequently, a sidewall (Si3 N4 film) 11, consisting of a material having a higher etching selection ratio for the oxide film 3, is formed at the sidewall of the wiring layer 9. Next, an interlayer insulating film 13 is deposited on the sidewall 1 and wiring layer 9. Thereafter, a third connecting hole 19 located on the wiring layer 9 is formed to the insulating film 13, without preparing allowance for the overlap of the pattern with the first wring layer 9 by etching the insulating film 13. Next, a third wiring layer 20 is formed within the third connecting hole 19.