VERIFICATION CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a verification circuit for a semiconductor integrated circuit, in which an influence is verified when a signal on which jitters or wonders are superposed by a simulation is inputted to the semiconductor integrated circuit, and in which an environment close to the condition of an LSI tester in a storing operation can be realized. SOLUTION: Outputs (a) to (d) of a plurality of kinds of delay circuits 1 to 4 whose delay amount is different are inputted to a selector circuit 6. The output of a selection signal generator 5 by which an aperiodic selection signal is generated in a test mode is inputted to the selector circuit 6. Respective outputs of the delay circuits 1 to 4 are selected aperiodically so as to be outputted according to the output of the selection signal generator 5 in the test mode. As a result, a signal whose phase is shifted aperidically is inputted to a semiconductor integrated circuit for verification.