MEMORY CELL DEVICE, MANUFACTURE THEREOF, AND OPERATING METHOD THEREOF

PROBLEM TO BE SOLVED: To enable a memory cell device of high memory density required for an electronic device in a gigabit generation by a method, wherein a large number of memory cells that are each provided with a selective transistor connected to a memory element are provided, and the memory cells are controlled via first word lines and second word lines which intersect each other. SOLUTION: A semiconductor pillar demarcated with a first and a second trench 110 comprises two memory cells. The memory cell is equipped with a common first selection transistor composed of a bit line 13', a first N -doped region 118, a first P-doped silicon layer 14, a first gate dielectric body 111', and a first word line 112'; and a second selection transistor composed of the first N -doped region 118, the second N -doped region 119, a second doped silicon layer 15, a second dielectric layer 114, and a second word line 115. The memory cells are controlled via the first word line 112' and the second word line 115.