TEST CIRCUIT

PROBLEM TO BE SOLVED: To provide a test circuit where the increase in a circuit scale is minimized. SOLUTION: On a test mode, inverted output QB of an F/F 2 is inputted to data input D of the F/F 2 to set a selection signal (b) of a selector circuit 1 to 'H', and a waveform with the I/2 frequency of a clock input waveform (c) of the F/F 2 is outputted from the F/F 2 (d). When the F/F 2 that does not operate due to a test pattern for selecting a semiconductor integrated circuit or has a low operation rate exists, the selector circuit 1 is connected to the data input D of the F/F 2 and the inverted output QB of the F/F 2 is inputted to the data input D of the F/F 2 on a test mode, thus operating the F/F 2 in a toggle for doubling the frequency and operating a group of logic circuits.