SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND ITS OUTPUT CONTROL METHOD

PROBLEM TO BE SOLVED: To provide a double data rate(DDR)-mode semiconductor memory device which is provided with a single data rate(SDR)-mode input/output function. SOLUTION: A first memory core 10 holds a plurality of data. Among from the plurality of data, the data which is addressed by a row address and by a first column address is output to a first data line 19a. A second memory core 20 holds a plurality of data. Among from the plurality of data, the data which is addressed by a row address and by a second column address is output to a second data line 19b simultaneously with the first memory core 10. By a control signal generation part 32, a first clock whose cycle is at the integral multiple of an external system clock and a second clock whose cycle is at twice the first clock are generated. Either the first clock or the second clock is output as an internal clock. An amplifying and multiplexing circuit 24 is operated in synchronization with the internal clock, it receives the data to be output from the first and second memory cores 10, 20, it amplifies and multiplexes the data, and it outputs the multiplexed data. Thereby, it is possible to support both an SDR mode and a DDR mode.