DATA PROCESSOR HAVING VARIABLE LENGTH CODE PROCESSING MECHANISM

PROBLEM TO BE SOLVED: To execute VLC decode processing and VLC encode processing through a little instruction steps by loading variable length code data to a buffer register and shifting them out of the buffer register. SOLUTION: All the load/store width of BR0 and BR1 is assumed as 32 bits. In the decode processing, a left shift instruction designates a shift amount as an operand and shifts data to left just for the designated amount. Similarly, the value of OFFR is incremented just for the shift amount. When the value of OFFR is more than 32, a conditional load instruction loads the data of 32 bits on a memory with the value of AR as an address onto the BR1. and increments the value of AR just for 4. When the value of OFFR is more than 32, a conditional left shift instruction shifts the BR1 to left just for (OFFR-32) bits and replaces the part of (OFFR-32) bits of the BR0 with shifted-out bits. At the same time, the OFFR is decremented just for 32.