MULTI-BUS MULTIPLEX COMMUNICATION ADAPTOR FOR DSP BASE

PROBLEM TO BE SOLVED: To distribute the operation that processes transmission data of a primary speed by making a host processor read information from 2nd data memory when an interrupt is received. SOLUTION: Although 16-bits in a HBRIDGE interrupt register are usually used to represent different types of services up to sixteen, a digital signal processor(DSP) 12 sends a control block of data that represents an interrupt to be requested to a prescribed area in data memory of a controller card 4 by direct memory access process. Therefore, DSP subsystems 12 set a certain bit to send an interrupt through PCI buses 48 and 53. When the interrupt is received through an interrupt A line, a controller processor 53a decides that a DSP subsystem 12-0 requested the interrupt, and when the interrupt is received through an interrupt B line, it decides that one of DSPs 12-1 to 12-7 requested it.