HIGH AND LOW SPEED OUTPUT BUFFER HAVING CONTROLLED SLEW RATE

PROBLEM TO BE SOLVED: To suppress the current of a short circuit and the ground bounce by delaying the drive of an output terminal by the complementary voltage via a 2nd driver until a 1st driver starts to complementarily drive the output terminal to respond to the transition of the logical value and then delaying the 2nd driver when the mode signal shows the highest speed mode. SOLUTION: When an input signal D is set at 0, the inverters I1 to I7 output logical value 1 respectively. The transistors TR P0, P1 and P2 are turned off and the TR N0, N1 and N2 are turned on to supply the drive current to an output terminal pad Q and to keep the voltage level of the pad Q at a low voltage power supply bus Vss. When the signal D is set at 1, the TR P0 to P2 supply the drive current to the pad Q to keep the voltage level of the pad Q at a high voltage power supply bus Vdd. Then FSB=0, FS=1, LSB=1 and LS=0 are satisfied during a highest speed mode operation, and the inverters I3 and I5 are disabled in a tri-state.