MEMORY CHIP PACKAGE
PROBLEM TO BE SOLVED: To protect I/O lead wires from an obstacle due to alpha particles by a method wherein memory chips are respectively provided with a semiconductor charge storage site, the soldered interconnection of the memory chips with a substrate for interconnection use is made within a spec...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To protect I/O lead wires from an obstacle due to alpha particles by a method wherein memory chips are respectively provided with a semiconductor charge storage site, the soldered interconnection of the memory chips with a substrate for interconnection use is made within a specified value from the charge storage sites and a solder material has a specified lead content. SOLUTION: A plurality of bonded semiconductor chips 12, 13 and 14 are provided on a substrate 11 for interconnection use. The chips 12 and 13 are memory chips and the chip 14 is a logic chip. The memory chips 12 and 13 are respectively provided with a semiconductor charge storage site and are mounted on the substrate 11 using a soldered connection. The soldered interconnection of the chips 12 and 13 with the substrate 11 is made within the extent of at least 5 mills, that is, 0.127 mm, from the semiconductor charge storage sites. Moreover, the lead content of a solder material is less than 5%. As a solder to be used for bonding the chips 12 and 13 to the substrate 11 in such a way, one hardly contains an alpha particle radioactive material is used. |
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