FREQUENCY SYNTHESIZER

PROBLEM TO BE SOLVED: To provide a frequency synthesizer with a high-speed lock-up operation and excellent frequency stability. SOLUTION: In this frequency synthesizer 1, a fraction frequency division control circuit 38 cyclically changes the frequency division value of a frequency divider 32 and turns external output signals OUT to a frequency for which the frequency of reference clock signals is multiplied by an average frequency division value. After the external output signals OUT are stabilized at its frequency, latch gate circuits 31 and 32 transmit signals outputted by a phase comparator 34 to a charge pump circuit 35 only for a period when the phase of the signals for comparison outputted by the frequency divider 32 is to match with the phase of the reference clock signals, hold the signals and output the held signals for the other period and thus, a ripple current is not included in the output of the charge pump circuit 35. At this.time, a compensation current is not superimposed on the output of the charge pump circuit 35.