QPSK DEMODULATOR

PROBLEM TO BE SOLVED: To enter into the normal synchronous state in the early stage at the time of reception channel change by eliminating the pseudo synchronous state of a QPSK demodulation part with a small-scale circuit constitution. SOLUTION: An inputted frequency multiplexed QPSK signal is subj...

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Bibliographische Detailangaben
Hauptverfasser: OTA KAZUHIRO, SHIOMI TOMONORI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To enter into the normal synchronous state in the early stage at the time of reception channel change by eliminating the pseudo synchronous state of a QPSK demodulation part with a small-scale circuit constitution. SOLUTION: An inputted frequency multiplexed QPSK signal is subjected to frequency conversion by a mixer 2 and is demodulated by a QPSK demodulation part 4, and its output is inputted to a Viterbi decoding part 5 and is outputted to a demodulation output terminal 6 after error correction. A minimum value of a path metric value outputted from the Viterbi decoding part 5 is compared with a threshold by a comparator 12; and if the pseudo synchronous state is discriminated, a local oscillator frequency setting part 13 is started and is operates to offset a local oscillator 3 by ±(baud rate)/4, thus leading the QPSK demodulation part 4 in the pseudo synchronous state to the normal synchronous state. The offset value for the normal synchronous state is stored in a memory 14, and the offset value stored in the memory 14 is added at the time of changing a reception channel.