DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To obtain a decoder circuit which reduces a power consumption and which enhances an operating speed by reducing a load which is applied to an X-decoder. SOLUTION: When, in order to select only one cell string out of many cell strings ST10 to ST80, a NOR gate input signal A and a NOR gate input signal B to one switching circuit selected from many switching circuits 100 to 800 are in a mutually opposite state, an input signal A and an input signal B to the remaining switching circuits are set surely to a LOW state. Consequently, through one switching circuit corresponding to the selected cell string, output signals at output ends C to R of a word line decoder 90 are transferred to only one selected cell string. However, inside the other switching circuits, the output signal of the decoder 90 is not transferred to input ends of word-line selection signals ML0 to WL15 at the cell strings which are not selected. Thereby, the number of loads due to the output ends C to R of one decoder 90 is reduced.