CONTROLLER

PROBLEM TO BE SOLVED: To attain failure analysis by preventing reset by a watch dog part without deteriorating the reliability or workability of a system when the watch dog part stops or recovers the outputting function of a reset signal, based on the output of an interface part. SOLUTION: A failure analysis signal is inputted to an interface part 14, decoded, and outputted to a CPU 10. The CPU 10 which receives a watch dog stopping instruction outputs the stopping signal of a watch dog function. This stopping signal is inputted through a parallel inputting circuit 11 to the control terminal of a buffer circuit 12, the output of the buffer circuit 12 is turned into a high impedance, and a reset circuit 13 is turned into an inactive state. Next, the CPU 10 which receives a failure analyzing instruction operates a prescribed failure analysis. At this point, the watch dog function is in the inactive state so that write and read for a memory can be attained without considering the watching dog function.