MULTIPLYING CIRCUIT FOR FLOATING POINT

PROBLEM TO BE SOLVED: To reduce the circuit size of a multiplying circuit for floating point. SOLUTION: The multiplying circuit is provided with an exclusive OR circuit 11 for outputting the code part SC of a product C from the code part SA of a value A and the code part SB of a value B. The circuit...

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1. Verfasser: SOTOZONO YAYOI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce the circuit size of a multiplying circuit for floating point. SOLUTION: The multiplying circuit is provided with an exclusive OR circuit 11 for outputting the code part SC of a product C from the code part SA of a value A and the code part SB of a value B. The circuit includes also a multiplier 31 for multiplying the mantissa part FA of the value A by the mantissa part FB of the value B, a normalizing circuit 35 for normalizing the multiplied result of the multiplier 31 and outputting the mantissa part FC of the product C, an adder 21 for adding the exponential part of the value A to the exponential part EB of the value B, and an incrementer 23 for correcting the added result of the adder 21 in accordance with a signal outputted from the circuit 35 and outputting the exponential part EC of the product C. The multiplier 31 finds out partial products by a secondary Booth decoder and a selector to add the partial products like an array type.