SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To realize a stable operation with a minimum design margin. SOLUTION: To a power supply terminal of an integrated circuit device (LSI) 1, supply voltage from a secondary battery 2 is supplied through a DC/DC converter 3. And the LSI 1 is provided with a delay monitor circuit 3,...

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Bibliographische Detailangaben
1. Verfasser: SONEDA MITSUO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To realize a stable operation with a minimum design margin. SOLUTION: To a power supply terminal of an integrated circuit device (LSI) 1, supply voltage from a secondary battery 2 is supplied through a DC/DC converter 3. And the LSI 1 is provided with a delay monitor circuit 3, a delay circuit (τ) 5, a phase-comparison circuit 6 and a integration circuit 7, etc., which are formed with the same gate circuit, etc., as a circuit of an original process route in the same process. Then an arbitrary operation clock is supplied through a terminal 8, and the clock is supplied to one input of the phase-comparison circuit 6 through a series circuit of the delay monitor circuit 4 and the delay circuit 5. Furthermore, the crock from the terminal 8 is supplied to the the input of the phase-comparison circuit 6, also. Further, a comparison output of the phase-comparison circuit 6 is supplied to the integration circuit 7, and an integration output thereof is supplied to the DC/DC converter 3 through a terminal 9.