LAYOUT METHOD FOR SEMICONDUCTOR
PROBLEM TO BE SOLVED: To prevent a semiconductor from faulty performance or degradation of a yield by holding data of a unit frequency of each cell and an electric current per unit load capacity and of minimum operating voltage which does not hinder the performance of the cell and by making placemen...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To prevent a semiconductor from faulty performance or degradation of a yield by holding data of a unit frequency of each cell and an electric current per unit load capacity and of minimum operating voltage which does not hinder the performance of the cell and by making placement and routing based upon the data. SOLUTION: After placing an enforced electric power (S1 ), a unit frequency of a circuit, an electric current of each cell per a unit load capacity and an electric current total value between the enforced electric power are calculated during auto placement and routing (S2 ) and an electric power voltage descending value per each cell is calculated by a distance of the enforced electric power and a width of a cell electric power (S3 ). The obtained electric power voltage descending value and an electric power voltage allowance value are compared (S4 ), the auto placement and routing is finalized (S5 ) in the case of the obtained electric power voltage descending value being lower than an electric power voltage allowable value. Conversely with the obtained electric power voltage descending value being larger than an electric power voltage allowance value, a possibility of the auto placement and routing is judged (S6 ), and the auto placement and routing is stopped (S7 ). |
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