PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE
PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host...
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creator | TANAKA KENICHI MITSUISHI ATSUSHI MAKITA JUNKO TSUBOTA HIRONO |
description | PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host computer 1 is connected through a bus 3 with a processor board 2, and provided with a memory 4 having a cache table 6 for managing data transfer to a processor board 2 and a data transfer processing part 5 for transferring data. The processor board 2 is provided with a memory 7 and plural processors 8, and a program is executed while necessary data are transferred with the host computer 1. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH10320364A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH10320364A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH10320364A3</originalsourceid><addsrcrecordid>eNrjZPANcAxy9PFx9VEICPJ3dg0O9vRzVwiODA5x9VVwcQ3zdHZVcPRzUXBxDHFUcHZ09gBJ-7qGePi7KLj5BymEeLgqBDv6ukLV8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK8AD0MDYyMDYzMTR2Ni1AAAtoAt1A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE</title><source>esp@cenet</source><creator>TANAKA KENICHI ; MITSUISHI ATSUSHI ; MAKITA JUNKO ; TSUBOTA HIRONO</creator><creatorcontrib>TANAKA KENICHI ; MITSUISHI ATSUSHI ; MAKITA JUNKO ; TSUBOTA HIRONO</creatorcontrib><description>PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host computer 1 is connected through a bus 3 with a processor board 2, and provided with a memory 4 having a cache table 6 for managing data transfer to a processor board 2 and a data transfer processing part 5 for transferring data. The processor board 2 is provided with a memory 7 and plural processors 8, and a program is executed while necessary data are transferred with the host computer 1.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19981204&DB=EPODOC&CC=JP&NR=H10320364A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19981204&DB=EPODOC&CC=JP&NR=H10320364A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TANAKA KENICHI</creatorcontrib><creatorcontrib>MITSUISHI ATSUSHI</creatorcontrib><creatorcontrib>MAKITA JUNKO</creatorcontrib><creatorcontrib>TSUBOTA HIRONO</creatorcontrib><title>PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE</title><description>PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host computer 1 is connected through a bus 3 with a processor board 2, and provided with a memory 4 having a cache table 6 for managing data transfer to a processor board 2 and a data transfer processing part 5 for transferring data. The processor board 2 is provided with a memory 7 and plural processors 8, and a program is executed while necessary data are transferred with the host computer 1.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPANcAxy9PFx9VEICPJ3dg0O9vRzVwiODA5x9VVwcQ3zdHZVcPRzUXBxDHFUcHZ09gBJ-7qGePi7KLj5BymEeLgqBDv6ukLV8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK8AD0MDYyMDYzMTR2Ni1AAAtoAt1A</recordid><startdate>19981204</startdate><enddate>19981204</enddate><creator>TANAKA KENICHI</creator><creator>MITSUISHI ATSUSHI</creator><creator>MAKITA JUNKO</creator><creator>TSUBOTA HIRONO</creator><scope>EVB</scope></search><sort><creationdate>19981204</creationdate><title>PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE</title><author>TANAKA KENICHI ; MITSUISHI ATSUSHI ; MAKITA JUNKO ; TSUBOTA HIRONO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH10320364A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>TANAKA KENICHI</creatorcontrib><creatorcontrib>MITSUISHI ATSUSHI</creatorcontrib><creatorcontrib>MAKITA JUNKO</creatorcontrib><creatorcontrib>TSUBOTA HIRONO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TANAKA KENICHI</au><au>MITSUISHI ATSUSHI</au><au>MAKITA JUNKO</au><au>TSUBOTA HIRONO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE</title><date>1998-12-04</date><risdate>1998</risdate><abstract>PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host computer 1 is connected through a bus 3 with a processor board 2, and provided with a memory 4 having a cache table 6 for managing data transfer to a processor board 2 and a data transfer processing part 5 for transferring data. The processor board 2 is provided with a memory 7 and plural processors 8, and a program is executed while necessary data are transferred with the host computer 1.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE |
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