PARALLEL PROCESSING SYSTEM DEVICE AND DATA CACHING METHOD FOR THE SAME DEVICE

PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TANAKA KENICHI, MITSUISHI ATSUSHI, MAKITA JUNKO, TSUBOTA HIRONO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To attain efficient data transfer by reducing overhead due to unnecessary data transfer between memory hierarchies generated when the size of data is larger than the management unit of a memory in a system in which more than two processing units are connected. SOLUTION: A host computer 1 is connected through a bus 3 with a processor board 2, and provided with a memory 4 having a cache table 6 for managing data transfer to a processor board 2 and a data transfer processing part 5 for transferring data. The processor board 2 is provided with a memory 7 and plural processors 8, and a program is executed while necessary data are transferred with the host computer 1.