INPUT CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To eliminate the need for newly providing power-down testing pins in the power-down condition of an input circuit, identify the function of a circuit connected to a subsequent stage without fixing the output level of the input circuit and accurately measure a DC consumed curren...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To eliminate the need for newly providing power-down testing pins in the power-down condition of an input circuit, identify the function of a circuit connected to a subsequent stage without fixing the output level of the input circuit and accurately measure a DC consumed current in the non-operated condition of an integrated circuit. SOLUTION: When a signal REF of power potential VDD or more is input to an input terminal 32 during a power-down mode, testing signals S54, S55 output from a power-down switching circuit 50 are activated to turn off a NMOS 45 in a sense amplifier 40 and put clocked inverters 61, 62 into a high impedance condition. Input signals IN input to the input terminal 31 are reversed in sequence by a clocked inverter 63 and an inverter 64 so that output signals OUT with the positive logicality to the input signals IN can be output from an output terminal 33. |
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