MANUFACTURE OF LEAD-ON CHIP SEMICONDUCTOR PACKAGE

PROBLEM TO BE SOLVED: To improve reliability by reducing the number of bonding interfaces between a semiconductor chip and a lead frame. SOLUTION: First, a read frame 120 having a plurality of internal leads 122 and a plurality of external leads 124 is provided. Next, liquid adhesive having a predet...

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Bibliographische Detailangaben
Hauptverfasser:	HO SEIKO, KIN HEIBAN, SAI ICHIKO, KIN SHIN
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To improve reliability by reducing the number of bonding interfaces between a semiconductor chip and a lead frame. SOLUTION: First, a read frame 120 having a plurality of internal leads 122 and a plurality of external leads 124 is provided. Next, liquid adhesive having a predetermined viscosity is applied to lower surfaces of the inner leads 122. Then, an active surface 112 of a semiconductor chip 110, where a plurality of electrode pads 114 are formed, is provided under the adhesive-applied lead frame 120, and the semiconductor chip 110 and the lead frame 120 are positioned with each other, such that each electrode pad 114 is exposed in space between adjacent inner leads 122. Next, the active surface 112 of the semiconductor chip 110 are bonded to the inner leads 122 of the lead frame 120 with the adhesive.