POWER SAVING CIRCUIT

PROBLEM TO BE SOLVED: To reduce power consumption without lowering an operation speed by supplying CPU clocks from a maximum operation clock transmitter in the case that the power consumption raised from under maximum power consumption set beforehand. SOLUTION: This circuit is provided with the maxi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: OUCHI YASUSHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To reduce power consumption without lowering an operation speed by supplying CPU clocks from a maximum operation clock transmitter in the case that the power consumption raised from under maximum power consumption set beforehand. SOLUTION: This circuit is provided with the maximum operation clock transmitter 6 for supplying first clocks for operating a CPU 1 with maximum ability, a 1/2 frequency divider 7 for frequency-dividing the maximum operation clocks into 2 and outputting them as second clocks for a low power consumption operation and a selector 8 for switching supply operation clocks to the CPU 1 to the maximum operation clocks or the ones from the 1/2 frequency divider 7 by output signals from a current detection circuit 4, etc. Then, the CPU clocks are supplied from the 1/2 frequency divider 7 in the case that the present power consumption becomes less than the ratio of the maximum power consumption set beforehand and the CPU clocks are supplied from the maximum operation clock transmitter 6 in the case that the present power consumption raised from under the ratio of the maximum power consumption set beforehand.