MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To increase the thickness of the whole dielectric layer and to prevent the electrostatic capacity of a capacitor from being decreased by a method wherein a high dielectric metallic compound layer is made to interpose between a silicon lower electrode and an upper electrode on t...
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creator | KYO KEIKUN LEE JUNG-KYU KOH YOUNG-LARK |
description | PROBLEM TO BE SOLVED: To increase the thickness of the whole dielectric layer and to prevent the electrostatic capacity of a capacitor from being decreased by a method wherein a high dielectric metallic compound layer is made to interpose between a silicon lower electrode and an upper electrode on the silicon lower electrode and the upper electrode is formed on the metallic compound layer. SOLUTION: A photoresist pattern is removed from a substrate 10 and an HGS layer is formed on the surface of a lower electrode 26. The removal of the photoresist pattern is conducted by a stripping or an ashing. It is preferable that the HGS layer is formed by feeding continuously silicon gas in a furnace in a thermal wall system of a process. This process is executed for widening the charging area of a capacitor to increase the electrostatic capacity of the capacitor without depending upon the characteristics of a dielectric layer. A metal silicide layer 29 is formed on the surface of the electrode 26 on the substrate 10 by a heat-treatment and moreover, a residual metal layer, which is not silicified and is located on the periphery of the electrode 26, is removed by a wet etching, whereby the final lower electrode of the capacitor is formed. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH10233493A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH10233493A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH10233493A3</originalsourceid><addsrcrecordid>eNrjZDDwdfQLdXN0DgkNclXwd1NwdgxwdPYM8Q9S8PRTCHb19XT293MJdQYJuLiGeTq78jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK8AD0MDI2NjE0tjR2Ni1AAAMhQmdw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>KYO KEIKUN ; LEE JUNG-KYU ; KOH YOUNG-LARK</creator><creatorcontrib>KYO KEIKUN ; LEE JUNG-KYU ; KOH YOUNG-LARK</creatorcontrib><description>PROBLEM TO BE SOLVED: To increase the thickness of the whole dielectric layer and to prevent the electrostatic capacity of a capacitor from being decreased by a method wherein a high dielectric metallic compound layer is made to interpose between a silicon lower electrode and an upper electrode on the silicon lower electrode and the upper electrode is formed on the metallic compound layer. SOLUTION: A photoresist pattern is removed from a substrate 10 and an HGS layer is formed on the surface of a lower electrode 26. The removal of the photoresist pattern is conducted by a stripping or an ashing. It is preferable that the HGS layer is formed by feeding continuously silicon gas in a furnace in a thermal wall system of a process. This process is executed for widening the charging area of a capacitor to increase the electrostatic capacity of the capacitor without depending upon the characteristics of a dielectric layer. A metal silicide layer 29 is formed on the surface of the electrode 26 on the substrate 10 by a heat-treatment and moreover, a residual metal layer, which is not silicified and is located on the periphery of the electrode 26, is removed by a wet etching, whereby the final lower electrode of the capacitor is formed.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980902&DB=EPODOC&CC=JP&NR=H10233493A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980902&DB=EPODOC&CC=JP&NR=H10233493A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KYO KEIKUN</creatorcontrib><creatorcontrib>LEE JUNG-KYU</creatorcontrib><creatorcontrib>KOH YOUNG-LARK</creatorcontrib><title>MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To increase the thickness of the whole dielectric layer and to prevent the electrostatic capacity of a capacitor from being decreased by a method wherein a high dielectric metallic compound layer is made to interpose between a silicon lower electrode and an upper electrode on the silicon lower electrode and the upper electrode is formed on the metallic compound layer. SOLUTION: A photoresist pattern is removed from a substrate 10 and an HGS layer is formed on the surface of a lower electrode 26. The removal of the photoresist pattern is conducted by a stripping or an ashing. It is preferable that the HGS layer is formed by feeding continuously silicon gas in a furnace in a thermal wall system of a process. This process is executed for widening the charging area of a capacitor to increase the electrostatic capacity of the capacitor without depending upon the characteristics of a dielectric layer. A metal silicide layer 29 is formed on the surface of the electrode 26 on the substrate 10 by a heat-treatment and moreover, a residual metal layer, which is not silicified and is located on the periphery of the electrode 26, is removed by a wet etching, whereby the final lower electrode of the capacitor is formed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDwdfQLdXN0DgkNclXwd1NwdgxwdPYM8Q9S8PRTCHb19XT293MJdQYJuLiGeTq78jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK8AD0MDI2NjE0tjR2Ni1AAAMhQmdw</recordid><startdate>19980902</startdate><enddate>19980902</enddate><creator>KYO KEIKUN</creator><creator>LEE JUNG-KYU</creator><creator>KOH YOUNG-LARK</creator><scope>EVB</scope></search><sort><creationdate>19980902</creationdate><title>MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE</title><author>KYO KEIKUN ; LEE JUNG-KYU ; KOH YOUNG-LARK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH10233493A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KYO KEIKUN</creatorcontrib><creatorcontrib>LEE JUNG-KYU</creatorcontrib><creatorcontrib>KOH YOUNG-LARK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KYO KEIKUN</au><au>LEE JUNG-KYU</au><au>KOH YOUNG-LARK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE</title><date>1998-09-02</date><risdate>1998</risdate><abstract>PROBLEM TO BE SOLVED: To increase the thickness of the whole dielectric layer and to prevent the electrostatic capacity of a capacitor from being decreased by a method wherein a high dielectric metallic compound layer is made to interpose between a silicon lower electrode and an upper electrode on the silicon lower electrode and the upper electrode is formed on the metallic compound layer. SOLUTION: A photoresist pattern is removed from a substrate 10 and an HGS layer is formed on the surface of a lower electrode 26. The removal of the photoresist pattern is conducted by a stripping or an ashing. It is preferable that the HGS layer is formed by feeding continuously silicon gas in a furnace in a thermal wall system of a process. This process is executed for widening the charging area of a capacitor to increase the electrostatic capacity of the capacitor without depending upon the characteristics of a dielectric layer. A metal silicide layer 29 is formed on the surface of the electrode 26 on the substrate 10 by a heat-treatment and moreover, a residual metal layer, which is not silicified and is located on the periphery of the electrode 26, is removed by a wet etching, whereby the final lower electrode of the capacitor is formed.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | MANUFACTURE OF CAPACITOR IN SEMICONDUCTOR DEVICE |
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