SEMICONDUCTOR TEST DEVICE
PROBLEM TO BE SOLVED: To contrive a saving space and small power consumption by amplifying or attenuating a desired signal only by the addition circuit of a small number of parts, and performing the test of a high voltage I/O pin. SOLUTION: In the case where an addition circuit having a signal proce...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To contrive a saving space and small power consumption by amplifying or attenuating a desired signal only by the addition circuit of a small number of parts, and performing the test of a high voltage I/O pin. SOLUTION: In the case where an addition circuit having a signal processing means 71 and a signal restoration means 72 is used, a switch Sa is turned off to turn on switches S1, Sb. When a signal is applied to a high voltage I/O pin connected to the switch Sb, switches S2, S3 are turned on to turn off a switch S4. The output signal of a driver 51 is input through the switches S1, S2 to the signal processing means 71. After the output signal of the signal processing means 71 is buffered by a buffer B1, it is applied to the high voltage I/O pin of a device to be tested 92 through the switches S3, Sb. The high voltage output signal of the high voltage I/O pin of the device to be tested 92 is input to the signal restoration means 72 through the switch Sb and a buffer B2. In the signal restoration means 72, it is attenuated to desired voltage and output or a level shift is performed into a desired voltage level. |
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