ROW DECODER FOR SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To provide a decoder circuit in which a word line enable-speed can be increased. SOLUTION: This device is provided with a main row decoder 70 selecting a main word line MWL in accordance with a row address in normal operation and disabling MWL in accordance with a blocking signal/CONCLK in row redundant operation, a section row decoder 80 receives an output of MRD 70 and a burst address in normal operation and driving a section word line SWL conforming to MWL, a redundant main row decoder 120 selecting a redundant main word line RMWL from an address control clock being the basis of a decoding signal of a row address and a blocking signal in row redundant operation, a redundant section row decoder 90 receives an output of RMRD 120 and a burst address and driving a redundant section word line rswl conforming to RMRD. As an address control clock is directly applied to a redundant main row decoder, increasing WL enable-speed can be achieved.