AMPLIFIER CIRCUIT

PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of improving reliability with a simple configuration by preventing destruction of a GaAs FET through the adoption of the configuration of always applying a voltage sequentially in the order of a gate and a drain in the amplifier circuit u...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: OKUBO YOICHI, KAGAYA NORIYUKI, FUJIMOTO SHOJI, HISAMATSU MINORU, NORICHIKA MICHIO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of improving reliability with a simple configuration by preventing destruction of a GaAs FET through the adoption of the configuration of always applying a voltage sequentially in the order of a gate and a drain in the amplifier circuit using the GaAs FET. SOLUTION: A drain of a P-channel junction transistor(TR) (JFET) 10 is connected to a drain of a GaAsFET 1, a bias voltage VCC is applied to a source of the JFET 10, a collector of an NPN TR 20 is connected to a gate of the JFET 10 and a base of the TR 20 connects to a ground level. If a voltage over an optional negative voltage (-VG) is not applied simultaneously to the emitter of the TR 20 and the gate of the GaAsFET 1, no bias voltage VCC is applied to the drain of the GaAsFET 1 in this amplifier circuit.