THREE PHASE CLOCK PULSE GENERATING CIRCUIT

PROBLEM TO BE SOLVED: To provide a three phase clock pulse generating circuit which performs a side panel display on 16:9 wide display element with a simplified peripheral circuit structure. SOLUTION: The output of 1/2 frequency dividing circuit 53 of source oscillation is provided with delay circui...

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Bibliographische Detailangaben
1. Verfasser:	TAKAHASHI KIMIYO
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION BASIC ELECTRONIC CIRCUITRY CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY EDUCATION ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY FREQUENCY-CHANGING NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION PULSE TECHNIQUE SEALS TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a three phase clock pulse generating circuit which performs a side panel display on 16:9 wide display element with a simplified peripheral circuit structure. SOLUTION: The output of 1/2 frequency dividing circuit 53 of source oscillation is provided with delay circuits 55 and 56, and the output of 1/4 frequency dividing circuit 54 of source oscillation is provided with delay circuits 57 and 58. A side panel mode screen and a full mode screen are driven by changing such switching of switches as to be appropriate timing between the times of the side panel mode and the full mode with a 1/3 frequency dividing reference signal 1 and the outputs of the circuits 53 and 54 being CPH1 through a switch 59 which switches them, a 1/3 frequency division delay signal 2 and the signals of the circuits 55 and 57 being CPH2 through a switch 60 which switches them, and a 1/3 frequency division delay signal 3 and the signals of the circuits 56 and 58 being CPH3 through a switch 61 which switches them.