REFERENCE CLOCK SUPPLY DEVICE AND TRAVELING OBJECT TERMINAL EQUIPMENT USING THE SAME

PROBLEM TO BE SOLVED: To attain low power consumption by stopping a VCTCXO as keeping bit synchronization and frame synchronization when no receiving operation is required in a reception awaiting state. SOLUTION: When the reception awaiting state is set, the value of a start value setting means 12 a...

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Bibliographische Detailangaben
Hauptverfasser: AIDA KOSAKU, TAKAHARA YASUAKI, KAWAI SATOSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To attain low power consumption by stopping a VCTCXO as keeping bit synchronization and frame synchronization when no receiving operation is required in a reception awaiting state. SOLUTION: When the reception awaiting state is set, the value of a start value setting means 12 and that of a return value setting means 13 are set, and when the count value of a counter means 11 matches the set value of the start value setting means 12, a binary counter 9 is stopped, and a symbol clock is stopped. The phase of the symbol clock at return time is found from the value in the binary counter 9 and it is written in the binary counter a. After the lape of a set time of a close time adjusting means 6, a gate means 5 is turned off, and power supply to the VCTCXO 2 is stopped. When the count value of the counter means 11 matches the set value of the return value setting means 13, the stoppage of the binary counter 9 is relased, and the power source is supplied to the VCTCXO 2, and after the lapse of a set time of a release time adjusting means 7, the gate means 5 is turned on, and the symbol clock is returned with a set phase by a reference clock.