SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a circuit for realizing a random access memory having different specification of input voltage level, output circuit GND current, clock access time, and power supply voltage (one or two power supply) in one product. SOLUTION: A circuit for altering the delivery time...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KOMIYAJI KUNIHIRO, NISHIO YOJI, HIRAISHI ATSUSHI, TOYOSHIMA HIROSHI, YAHATA HIDEJI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a circuit for realizing a random access memory having different specification of input voltage level, output circuit GND current, clock access time, and power supply voltage (one or two power supply) in one product. SOLUTION: A circuit for altering the delivery time of an output signal depending on an internally or externally generated control signal is provided. More specifically, the delay time of an internal clock signal CLK for controlling an output register is set equal to the delay time of one stage TM1 of a transfer circuit for one path and equal to the delay time of a delay circuit + one stage TM2 of the transfer circuit for another path. The delay time is switched by the internally or externally generated control signal.