MAIN MEMORY CONTROLLER

PROBLEM TO BE SOLVED: To provide a main memory controller substantially reduced in a series of operations such as the read of memory and the merging and write of data in a partial write processing to a main memory and improved in the performance of access to a main memory unit. SOLUTION: This controller is provided with address butters 26-29, comparators 30-33, data butters 37-40 and a selector merging control circuit 46. In the case that matching addresses are present as the result of comparison in the plural comparators 30-33, the selector merging control circuit 46 merges the data of the data butter and latest partial write data, re-holds them in a write data butter and performs control so as to write them in the main memory in the case that the data width of the data buffer becomes the full write width of the main memory.