COMPUTER FOR DELAY TIME BETWEEN DESIGNATED NODES IN INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To automatically compute the delay time between designated nodes, by providing a computer with a delay time adding means which adds the individual delay times computed by a cell delay time computing means and the individual delay time computed by a wiring delay time computing m...

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Hauptverfasser: OSAWA ISAKU, NARA HIDEYUKI, SATO HIDEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To automatically compute the delay time between designated nodes, by providing a computer with a delay time adding means which adds the individual delay times computed by a cell delay time computing means and the individual delay time computed by a wiring delay time computing means, and outputs the sum total as the delay time between a starting point node and an ending point node. SOLUTION: A node designating means 1 presents the relation of connection between cells to an operator, and the operator designates the starting point node and the ending point node by a mouth or a keyboard. A course retrieving means 2 retrieves the course between both nodes, based on the layout data L. A cell delay time computing means 3 computes the delay time of individual cells on the retrieval course, based on the delay property within a cell library C, and a wiring delay time computing means 4 computes the delay time of the wiring between individual cells on the retrieval course, based on the delay property of a CR circuit, referring to the process data p and layout data L. All delay time on the retrieval course is outputted as the addition result by the delay time adding means 5.